Frequently Asked Questions

• Q: Digital place and route? I thought you just did analog automation.
• A: Since we already had a placer, router, and simulation environment, we are now adding digital place and route. The widths will be automatically sized to meet timing based on input slopes, output load (including wire RC time constants), corners, and latch setup and holds. This is intended to be used for designs that are less than 100K gates per block, since we update the schematic with the updated information based on folding, buffer insertion, width adjustment, etc. Our focus remains with analog and mixed signal designs. Analog designs always have digital logic, such as encoders, decoders, analog switch logic, etc. We would be short-sighted if we did not address the digital parts of the flow that the mixed signal designer needs to face.
• Q: Do you generate the standard cells and characterize them?
• A: Yes. We generate the standard cells and characterization tables on the fly as you add the cells to the schematic. This provides the timing information for our placer and router.
• Q: Do you have digital and analog simulation capability?
• A: Yes. Launch Hspice, Msim, Gnucap (free, spice-like), IRsim (free, over 1000X faster than spice) from the schematic. View the waveforms in our waveform tool. Measurements, voltages, currents, and operating points (vod, vds-vdsat) are backannotated onto the schematics at any timepoint and corner. Co-simulation with verilogams is coming the first half of 2009.
• Q: Did you say complete layout automation?
• A: Yes. Press "A" to automatch (you can do this manually too), "P" to place. Press "R" to route. Bada bing, bada bang. Layout done! BTW: "O" optimizes.
• Q: Where is the full automation demo?
• A: Sorry, but we aren't going to show our competitors how to do it. You will need us to show you onsite.
• Q: What do we do with our overseas team that does layout?
• A: Cut them.
• Q: What should we do with our customization scripts written in SKILL?
• A: So you probably can layout an ADC in less than an hour too, RIGHT?!!! You probably simulate with the real parasitics at all times too, RIGHT?!!! So much for your scripts. We know what you want.
• Q: How do you set matching?
• A: You can do it manually by hitting "=" and the pair of devices to interdigitize, or hitting the clone icon, then matching devices/blocks. Ridiculously simple.
• Q: How many levels of hierarchy can you handle at a time?
• A: All levels.
• Q: How do you size the wires?
• A: We supply a simulation environment. We use Kirchoff's laws that were established in 1845.
• Q: Do you handle electromigration (EM)?
• A: Yes. DC, peak, RMS. http://en.wikipedia.org/wiki/Electromigration
• Q: Do you support GDSII?
• A: We save to Openaccess. We also ship the OA2GDS translator. Get it, dummy (PC)?
• Q: How do you compare with Cadence?
• A: Our tool is automatic. Enter the topology and testbench. We will automatch, autosize, place, and route. No scripts or pcell code required. We read in the technology rules and automate the entire process.

  Even in our manual mode, which isn't needed, Analog Rails is more powerful than Virtuoso, because Virtuoso is a drawing program. It relies on error checking tools once the layout is done. Users may as well use Photoshop and convert the format and run the same checkers. The parasitic estimations are also completely bogus.

  1) We don't allow violations to occur in the first place

  2) Your simulation results will always have the real parasitic values because layout is done in minutes.

  Stop drinking the Cadence Kool-aid. They are in cahoots with CAD groups that look to customize the environment to fit "their" needs. Do you use the built-in fonts from Microsoft Word, or do you have a team of people customizing it? Why isn't the automation built into the tool? Do you really think your Data Converter group is different than your competitors? C'mon, get over it. You ain't any different.

  We know what you want.

• Q: Are you complimentary to Virtuoso?
• A: We read the same database (Openaccess), so you can use both platforms at the same time.
• Q: Aren't you a startup company?
• A: No, you heard wrong. We started many years ago. We are an upstart company.
• Q: I just want to work on the schematic. Why is the layout tool always open?
• A: They must co-exist. Schematic changes are reflected in the layout instantly, and SA, SB, AD, AS, PD, and PS are reflected back into the schematic instantly. 2-way communications. Same with dummy devices. Add them to the layout with a mouse click, and they appear in the schematic. They share the same database.
• Q: What happens to the layout if I change my schematic?
• A: You may only change the preroute (don't worry, we always save a copy). Changes will automatically ripple throughout the layout, forcing compliance to the design rules. Once your are happy with your changes, either auto-route, or place and route.
• Q: Why do we need layout on the fly?
• A: For simulation accuracy. At feature sizes below 100n, SA and SB have a large effect. The bogus pre-layout calculations that are provided in cdf/pcalls are no longer going to cut it.
• Q: Why all the emphasis on simulation, I thought you were a layout tool company?
• A: Think again. Our expertise is in circuit design and simulation, but we also understand layout.
• Q: Can you handle 65n and other new processes?
• A: That is our specialty.
• Q: Where are the rulers?
• A: Why do you need them? Arails knows the design rules, just like Pac-Man knows where the wall is. We provide dX/dY.
• Q: You expect me to believe this is really "correct by construction?"
• A: http://www.correctbyconstruction.com ... see?
• Q: Can you give me more specifics about your automatic placer?
• A: It is router-aware, since our router developers are building it. Multiple results will be provided. Although we expect the placement will be good, the user can manually adjust the placement with its auto snap, abutment, and repel, then launch the router.
• Q: How about manual routing?
• A: Very powerful. Connectivity and DRC rule aware, collision avoidance, automatic via (with extension) insertion. Terminals light up during routing to show possible end points. Thicken wires a pitch at a time with a mouse click.
• Q: And the automatic router?
• A: Correct by Construction™. DRC/LVS correct, double vias, automatic well tap connection, density fill, gate and well protection diodes, and provide lots of solutions. Wires are automatically widened based on simulation results. We handle the new design rules down to 45n.
• Q: How about automatic router performance?
• A: It used to be slow. Now check us out!
• Q: Isn't an optimizer difficult to use?
• A: Not ours. It is completely integrated into the schematic. Click onto the checkbox next to the property, match the devices, place the predefined measures into the schematic, use our testbench templetes or build your own, then launch. We have 2 global and 2 local optimizers. Comes with free support.
• Q: How about differential signals/layouts?
• A: You specify the type of differential structure in the schematic and we generate and route it differentially with dummy extensions and sidewall shields. With analog as our first name, you better believe we can do this.
• Q: What if we don't want the shield?
• A: Too bad. You are getting the shield. If you want to lower the capacitance, increase the spacing, but you are getting the shield.
• Q: Do you have a constraint manager?
• A: Since we specialize in analog, we need to handle constraints, but you are not going to believe how easy it is to set them. There are much fewer things to setup than our competitors. We have a strong grasp of the obvious. "No brainer" constraints are built in. We make opinionated software, and we are biased towards the conservative side, so real estate savings is a lower priority than circuit performance. That being said, layouts can be smaller with our approach since you can be more aggressive on layout sizes because your simulations have taken the real layout values into account.
• Q: Can we just buy the pieces we need?
• A: No. The flow stays together, which consists of schematic, simulation environment, simulator (unlimited), optimizer, layout, placer, router, parasitic extractor. They play nicely together. Why separate them?
• Q: Can you read Virtuoso Technology files?
• A: Yes. We will also set up your process for free. It usually takes a day. Here is a snippet of the tech file format:
  num_metal_layers = 9
  mx_layer_start = 2
  mx_layer_end = 6
  my_layer_start = 7
  my_layer_end = 8
  mz_layer_start = 9
  mz_layer_end = 9
  vx_widthExact = 100
  pf_enclosure_co = 20
  m1_enclosure_co = 30
  m1_enclosureSidesTwo_co = 50
• Q: How do I make CDF's and PCELLS?
• A: The creation of pcells are trivial in Arails. Just set the valid layers that define the device and the surrounding layers. No code writing required. We handle mosfets, fringecaps, mimcaps, bipolars, resistors, differential pairs, mirrors, and all structures needed to build analog switchcap circuits. Here is an example of the CAD file for a pmos:
  define pmos4
  type pmos
  prefix mp
  netlist_prefix M
  param model type=string default=pmos4
  param m alias=m type=int min=1 default=1 ...
  display w l m
  term drain=D
  term source=S
  term gate=G
  term bulk=B
  layer pp drawing od pdiff enlarge pp_enclosure_od
  layer nw drawing od pdiff enlarge nw_enclosure_odp
  netlist hspice M@ $(drain) $(gate) $(source) $(bulk) &(model) l=&(l) w=&(w) m=&(m)
  netlist verilog-ams &(model) (.w=(&(w)), .l=(&(l)))) M@ (.d($(drain)), .g($(gate)), .s($(source)), .b($(bulk))); enddefine
• Q: Are you part of that silly pcell coalition?
• A: No. We are instead members of the Built-In Parameterized Cell Library (BIPL) coalition. We believe the user should just add the device and the tool should make the pcell without the need of a CAD group to create them. See CDF/PCELL question.
• Q: But our pcells and CDF's are modeled perfectly.
• A: HA HA HA! You still don't get it. No they weren't...now they are! The layout exists (hint...they are extracted from layout)
• Q: How about transmission lines?
• A: Coming in March, 2009.
• Q: We need to customize to meet our needs.
• A: Tell us what you think you need that we haven't already thought of.
• Q: I want this now! Gimme Gimme!
• A: Call us (408-455-3700)! Discussions must involve a SENIOR CIRCUIT DESIGNER.
• Q: Analog Rails? What's with the rails?
• A: Arails is a framework to create integrated circuits quickly. No steering needed. We know the direction you want to go in.
• Q: What is your sales strategy?
• A: Build it and they will come. This isn't like comparing the Betamax vs VHS. This is a power saw vs a handsaw. Our marketing sucks. We have no marketing nor sales force, and have no plans to get any. We have 1 sales guy. He is an analog circuit designer with no sales experience. He also writes specs and does payroll.
• Q: How do you handle support?
• A: We utilize telephone technology. E-mail, live chat, or logging into our bug/enhancement system works too. Our QA guys handle support.
• Q: How stable is your company?
• A: Let's do the math:
  We are automatic...They are manual.
  
  We have 12 people, mostly paid in stock...They have over 5000 people.
  
  We have no debt...They paid their former CEO over $10,000,000.
  
  We have no sales or marketing force, no middle management...They do.
  
  We are owned by our engineers/developers...they are owned by business investors.
  Conclusion: We are an engineering driven company whose developers aren't going anywhere, since this is their company. We are not driven by short term, fast buck decisions. We have a much more powerful tool than our competitors. Automation beats manual, so can beat our competitor at both the high end as well as overall cost of ownership.
• Q: What cheap labor area do you export your work to?
• A: We off-loaded work from Scottsdale to Chandler to take advantage of the cheaper labor rates.
• Q: We heard your development team in AZ are using illegal immigrants to write your software.
• A: We are located in AZ, but the hiring of illegal immigrants was a false rumor. We would never get away with it. You have heard of our sheriff, haven't you?
• Q: Why are the Cardinals so lousy?
• A: Most of our defense is at the border. McCain is looking into it.